A new set of 3D graphics and media processing instructions are being proposed by a group of enthusiasts. These new instructions are built on the RISC-V’s base vector instruction set. The extensions add support for entirely new data types that are specific to graphics.
RV64X Supports Vector, Texture, and Z-axis Operations
Pixel, vector, texture, and Z-axis and frame buffer operations are also supported. This new RISC-V-based ISA is basically a hybrid CPU/GPU Instruction Set Architecture. The team behind the project is calling it ‘RV64X’. This ISA’s instructions are 64-bit long because 32 bits simply isn’t enough to support an ISA as robust as this.
RV64X Isn’t The Only Game in Town
It’s a crowded space. There are plenty of GPU architectures out there to choose from already. But this group says that commercial GPUs (looking at you AMD and nVidia) are far less effective at meeting the obscure needs of some fields like adaptable HPC and dual-phase 3D frustum clipping.
The group thinks that collaboration will provide flexible standards. They also posit that it will drastically reduce the effort needed, and can help to avoid mistakes via cross-verification.
The researchers are saying that their goal is to create a small and area-efficient design that has custom programmability and extensibility. It plans to offer low-cost IP ownership and development.
The RV64X ISA is an Enhancement to Current Chips, Not a Replacement
They do not want to compete with commercial offerings. This new ISA can be implemented in ASIC and FPGA designs and it’s going to be open source and totally free. The first design is going to be aimed at low-power microcontrollers. It’s even going to be Vulkan-compatible, and will, in time, support other popular APIs such as DirectX and OpenGL.
The final silicon is going to be a RISC-V core that includes a GPU functional unit. From the programmer’s perspective, it’s going to look like a single piece of hardware that has 64-bit long instructions. The programming model is an apparent SIMD (Single Instruction Multiple Data), so the compiler generates SIMD from prefixed scalar opcodes.
The chip is going to include variable-issue, SIMD backend, vector front-end, branch shadowing, and precise exceptions. There isn’t going to be any need for an RPC or IPC calling mechanism to be able to send 3D API calls to and from the CPU to the GPU and vice-versa. The chip will be available in both 16-bit fixed point, and 32-bit floating-point versions.